This invention relates in general to circuit testers and relates more particularly to a method of utilizing a class of vector-specific test circuits to improve fault coverage without significantly increasing Input/Output (I/O) pin count and/or I/O pin sharing.
In all integrated circuit manufacturing processes, some fraction of integrated circuits (ICs) manufactured by such processes have one or more faults. The fraction of manufactured ICs that are good is referred to as the yield of the process. Because yields can be significantly below 100%, it is important to test these ICs for faults. Preferably, chips are tested after they are each mounted into the packaging that provides protection and interfacing for connection to other chips so that faults produced by the process of packaging the chips are tested along with the faults produced by the process of manufacturing the ICs.
One class of faults that are particularly important to test are the "stuck-at faults". These faults occur because of opens and/or shorts that result in a given node being stuck at zero or stuck at one, even though, in proper operation of the IC, it should achieve each of these values under appropriate circumstances.
In general, fault testing involves two separate components: (1) controlling the voltage on various circuit nodes and (2) testing to see if the actual voltages on such nodes equal the expected values. The first of these two components is referred to as the controllability component of fault testing and the second is referred to as the observability component of fault testing. To be able to apply test signals to the IC and to observe the responses of the IC to these signals, the ICs typically contain signal inputs and outputs, referred to as test points, to enable input of test signals to the IC and output of signals from the nodes being observed.
The typical manner of testing circuits for faults is illustrated in the following examples of fault tests of random access memories (RAMs). A typical RAM test sequence consists of a first phase of writing data to the RAM and a second phase of reading this data from the RAM and comparing it with expected data. During the first phase, the fault tester produces a first sequence of addresses and, for each generated address, also produces a data word that is written to the location identified by the generated address. During the second phase, the fault tester generates the same sequence of addresses and, for each generated address, the actual data in the location identified by that address is compared with the data that is supposed to be in that location.
In one particular manner, this class of fault tests is particularly simple -namely, there is no problem in controlling or observing the state of each memory element of the RAM. The RAM can be fully tested by filling it with all possible different combinations of data and, for each combination of stored data, checking to see that each piece of stored data is correct. However, since the number of these combinations for a RAM containing N M-bit memory locations is 2.sup.MN, even at the high clock rates available today, it would take an impracticably long time to enter all of these possible combinations. Therefore, carefully chosen subsets of these possible combinations are generated (typically in accordance with some algorithm) to test for particular classes of faults. RAM test algorithms are exemplified by the walking 1's, walking 0's, checkerboard and write address algorithms illustrated in FIGS. 1-4, respectively.
Fault testing of most circuits is more difficult and inherently less complete than is possible in fault tests of RAMs because of the difficulty and/or impossibility of controlling the value of every node that should be tested and of the difficulty and/or impossibility of observing the actual value that is stored on each such node. Fault simulation tests typically provide a list of those potential faults that are tested. However, whether because of limitations on the acceptable duration of fault tests or because of the inability to control and/or observe some of the circuit nodes of interest, fault tests will in general be incomplete. The fraction of possible faults that are actually tested by a given fault test is referred to as the "fault coverage" of such test.
In the article by Lawrence W. Goldstein, et al, entitled SCOAP: Sandia Controllability/Observability Analysis Program, a program is discussed that analyzes the controllability/observability problem of various circuits. Circuits are divided into two classes of circuits: combinational circuits in which the binary value of every node is uniquely determined at any given time by the data applied at that time on the input lines; and sequential (i.e., state-dependent) circuits that each includes memory elements (e.g., flipflops) so that, at any given time, the binary value of at least some of the circuit nodes depends not only on the input data at that time, but also on at least some previously applied input data and on the initial state of this circuit. Sequential circuits are particularly difficult to test because of the state-dependent nature of its response to test input. Fault tests for sequential circuits will therefore generally exhibit a lower fault coverage than will combinational circuits having a comparable number of components.
The article by Thomas W. Williams, et al entitled Design for Testability-A Survey, IEEE Transactions On Computers, vol. C-31, No. 1, January 1982, discusses a fault test technique, referred to as the Level-Sensitive Scan Design, that addresses the difficulty of testing sequential circuits. This technique utilizes a "shift register latch" to convert a network into a purely combinational circuit.
As circuit complexity and density has increased, the difficulty of generating test patterns and simulating faults has drastically increased. The article by Williams et al presents a number of other testing techniques and approaches, some of which are applicable to many circuits and others that are limited to narrow classes of circuits. One of these techniques addresses the problem that the duration of a fault test is approximately proportional to the number of logic gates to the power 3. In accordance with this technique, jumpers and/or gates are included in a circuit board to enable components on a circuit board to be isolated (i.e., "partitioned"). This enables each of these isolated components to be separately tested, thereby greatly reducing the time required for a fault test of the entire circuit board. For example, if the board consists of M components, each containing on the order of N logic gates, then a test of the entire circuit requires a time interval approximately proportional to (MN).sup.3. In contrast to this, a test of the isolated components requires a time proportional to M*(N.sup.3) which has reduced the test time by a factor of M.sup.2.
Because of the extremely large number of nodes of typical circuits manufactured today, it has gotten extremely difficult to access all of the nodes that need to be accessed either to apply test signals or that need to be observed to produce test output. It is also difficult to access all of these nodes through the limited number of test points that can be placed on a chip. As indicated in the article by Thomas W. Williams, et al, shift registers are often included in circuits to enable a string of test data to be output through a single output test point.
The problem of limited IC surface area available for input/output (I/O) test points is also addressed in U.S. Pat. No. 4,749,947 entitled Grid-Based, "Cross-Check" Test Structure For Testing Integrated Circuits, issued to Tuchar R. Gheewala on Jun. 7, 1988. This cross-check test structure utilizes a set of M horizontal probe lines that form a rectangular grid of intersections with a set of N vertical sense lines. This enables a rectangular array of MN test points, each located near one of these intersections, to be monitored. Only one probe line is activated at any given time. If the mth probe line is activated, then the test points adjacent to the mth row of intersections of the grid are each output to an associated one of the vertical sense lines. In other embodiments, the total number of input and output points required for fault testing can be reduced to 6 by use of various devices such as shift registers.